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TC93P24FG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC93P24FG
Single-Chip DTS Microcontroller (DTS-20)
The TC93P24FG is a single-chip digital tuning system (DTS) microcontroller incorporating a 230 MHz prescaler, PLL, and LCD driver. In addition to a 20-bit IF counter, an 8-channel, 8-bit AD converter, two types of serial interface, and buzzer function, the TC9324FG offers a range of functions required for DTS, including an interrupt function, an 8-bit timer-counter, and an 8-bit pulse counter. In addition, the LCD driver features six modes combining 1/4, 1/3, and 1/2 duty and 1/2 and 1/3 bias. This product is suitable for use in a wide variety of DTS systems, from automobile to home audio, including compact stereo systems. Weight: 1.6 g (typ.)
Features
* * * * CMOS DTS microcontroller LSI with built-in 230 MHz prescaler, PLL, and LCD driver Operating voltage: PLL operating: VDD = 4.0 to 5.5 V (typ. 5.0 V) PLL off: VDD = 3.5 to 5.5 V (when CPU only operating) Crystal oscillator frequency: 4.5 MHz, 75 kHz Current dissipation: PLL operating: IDD = 3 mA (typ.) (crystal oscillator frequency 4.5 MHz, VHF mode) PLL off: IDD = 1 mA (typ.) (crystal oscillator frequency 4.5 MHz, CPU only operating) PLL off:IDD = 0.3 mA (typ.) (crystal oscillator frequency 75 kHz, CPU only operating) Operating temperature range: Ta = -40 to 85C Program memory (ROM): 16 bits x 16,384 steps Data memory (RAM): 4 bits x 4,096 words Instruction execution time: 1.78 s (crystal oscillator frequency 4.5 MHz) 40 s (crystal oscillator frequency 75 kHz) Stack levels: 16 General-purpose IF counter: 20-bit (CMOS input supported) AD converter: 8 bits x 8 channels LCD driver: 1/4, 1/3, 1/2 duty, 1/2, 1/3 bias modes selectable, 136 segments maximum I/O ports: CMOS I/O ports: 40 Output-only ports: Up to 31. Input-only ports: Up to 5 Timer-counter: 8-bit (as timer clock: INTR1, INTR2, instruction cycle, 25kHz, or 1 kHz selectable) Pulse counter: 8-bit up/down counter (input from INTR2 pin) Buzzer: 0.625 to 3 kHz (8 settings) Four modes: Continuous, Single-Shot, 10-Hz Intermittent, 10-Hz Intermittent at 1-Hz Intervals Interrupts: 2 external, 4 internal (three types of serial interface, 8-bit timer) Package: QFP-100 (0.65-mm pitch)
* * * * * * * * * * * * * *
1
2006-08-31
TC93P24FG
Pin Assignment
P5-3 (SCK3/SCK4) P4-3 (SCK1/SCK2)
P5-2 (SO3/SO4)
P4-2 (SO1/SO2)
INTR2 (CTRIN)
P5-1 (SI3/SI4)
P4-1 (SI1/SI2)
P3-3 (ADIN8)
P3-2 (ADIN7)
P3-1 (ADIN6)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P6-1 P6-2 P6-3 P7-0 P7-1 P7-2 P7-3 P8-0 P8-1 P8-2 P8-3 VCPU GND4 XOUT2 XIN2 VDD4 XOUT1 XIN1 GND5 VEE
P3-0 (ADIN5)
P5-0 (BUZR)
DO2 (OUT)
IFIN2 (IN2)
IFIN1 (IN1)
TEST2
INTR1
MUTE
HOLD
GND3
GND2
TEST
AMIN
VPLL
FMIN
VDD3
VDD2
P6-0
P4-0
DO1
81 82 83 84 85 86 87 I/O ports
PLL
Interrupt input
SIO I/O ports
SIO
I/O ports AD converter (8 channels)
50 49 58 47 46 45 44
P2-3 (ADIN4) P2-2 (ADIN3) P2-1 (ADIN2) P2-0 (ADIN1) DCREF P1-3 P1-2 P1-1 P1-0 GND1
RESET (VPP) VDD1 P10-3 (S34) P10-2 (S33) P10-1 (S32) P10-0 (S31) P9-3 (S30) P9-2 (S29) P9-1 (S28) P9-0 (S27)
I/O ports 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 LCD driver (1/4, 1/3, 1/2 duty, 1/2, 1/3 bias, 136 segments max) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Oscillator 1 (4.5 MHz) Oscillator 2 (75 kHz) I/O ports QFP-100 (0.65-mm pitch) 43 42 41 40 39 38 37 36 35 34 33 32 31
OT5 (S1)
OT6 (S2)
OT7 (S3)
OT8 (S4)
OT3 (COM3/S36)
OT4 (COM4/S35)
OT9 (S5)
OT10 (S6)
OT11 (S7)
OT12 (S8)
OT13 (S9)
OT14 (S10)
OT15 (S11)
OT16 (S12)
OT17 (S13)
OT18 (S14)
OT19 (S15)
OT20 (S16)
OT21 (S17)
OT22 (S18)
OT23 (S19)
OT24 (S20)
OT25 (S21)
OT26 (S22)
OT27 (S23)
OT28 (S24)
OT29 (S25)
OT1 (COM1)
OT2 (COM2)
2
OT30 (S26)
2006-08-31
TC93P24FG
Block Diagram
MUTE TEST
Mute
Serial Interface-2 R/W Buf. P5-3 (SCK3/SCK4) P5-2 (SO3/SO4) Port5
Timer
HOLD
G-Reg.
INTR1 INTR2 (PCTRIN)
Interrupt Control RAM (4 x 4096 word)
P5-1 (SI3/SI4) ALU P5-0 (BUZR)
Up/Down Counter
Buzzer
IFIN1 (IN1) IFIN2 (IN2) GND3 FMIN AMIN
IF Counter
Data Register (16 bit)
Serial Interface-1
PLL Port4
P4-3 (SCK1/SCK2) P4-2 (SO1/SO2) P4-1 (SI1/SI2)
VPLL VDD3 DO1 DO2 (OUT) TEST2 P6-0 P6-3
VPLL One Time PROM Phase Comp. (16 x 16384 step) Port3 Instruction Decoder
P4-0 VDD2 GND2 P3-3 (ADIN8) P3-0 (ADIN5)
Port6
P2-3 (ADIN4) VPP Port2 P2-0 (ADIN1)
P7-0 P7-3
Port7
Program Counter
A/D Conv.
DCref
P8-0 P8-3
Port8
Stack Register (16 level)
Port1
P1-3 P1-0 GND1
VCPU GND4 XOUT2 XIN2 VDD4 XOUT1 XIN1 GND5 VEE
VPP VCPU Reset 75 kHz Oscilator OSC Cont. 4.5 MHz Oscilator RESET (VPP) VDD1 Port10 Peripheral Port9 P10-3 (S34) P10-0 (S31) P9-3 (S30) P9-0 (S27)
CPU
LCD Driver
Output Port
OT5 (S1)
OT6 (S2)
OT7 (S3)
OT8 (S4)
OT3 (COM3/S36)
OT4 (COM4/S35)
OT9 (S5)
OT10 (S6)
OT11 (S7)
OT12 (S8)
OT19 (S15)
OT20 (S16)
OT21 (S17)
OT22 (S18)
OT23 (S19)
OT24 (S20)
OT25 (S21)
OT26 (S22)
OT27 (S23)
OT28 (S24)
OT29 (S25)
OT1 (COM1)
OT2 (COM2)
3
OT30 (S26)
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TC93P24FG
Pin No. Symbol Pin Name Function and Operation Output ports. Pins OT1 to OT20 can be incremented by software, allowing easy data access to external RAM/ROM. Can be set to LCD driver output by software. At 1/4 duty, controller can display up to 136 segments using a matrix consisting of COM1 to 4 and SEG1 to 34. At 1/3 duty, can display up to 105 segments using a matrix consisting of COM1 to 3 and SEG1 to 35. At 1/2 duty, can display up to 72 segments using a matrix consisting of COM1 to 2 and SEG1 to 36. Set to output ports after a system reset or clock stop. Remarks
1
OT1/COM1 Output port /LCD common output
2
OT2/COM2
VDD VEEH /VEEM /VEEL
3
OT3/COM3 /S36 OT4/COM4 /S35 OT5/S1
Output port /LCD common output /LCD segment output
4
5~30
OT30/S26 P9-0/S27 31~34 P9-3/S30 ~ P10-0/S31 35~38 P10-3/S34 ~
Output port /LCD segment output
~
4-bit CMOS I/O ports. Input and output can be programmed I/O port 9 /LCD segment output in 1-bit units. These can be set bit by bit to LCD driver output by software. After a system reset, set to I/O port input. When a clock stop is executed, the I/O port 10 Input pins used as the LCD driver must be /LCD segment output set to output Low level (function as an instruction I/O port).
Device's system reset signal input pin. Setting RESET to Low level triggers a reset. When the pin is set to High, the program starts from address 0. Since system reset will start if a voltage beyond 0 V to 3.5 V is supplied to VDD pin, this pin is used by fixed at High level. This pin is used as program voltage supply for One Time PROM. In case of writing program into the internal PROM, 12.5 V is supplied to this pin. 4-bit CMOS I/O port. Input and output can be programmed in 1-bit unit.
VDD VEEH /VEEL
VDD
40
RESET /VPP
Reset input /Program voltage supply
VDD
P1-0 42~45 I/O port 1 Input instruction P1-3
~
4
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TC93P24FG
Pin No. Symbol Pin Name AD converter reference voltage input Function and Operation AD converter reference voltage input pin. Normally apply VDD. Remarks
46
DCREF
To AD converter
P2-0 /ADIN1 47~50 P2-3 /ADIN4
I/O port 2 /A/D analog voltage input
P3-0 /ADIN5 51~54 P3-3 /ADIN8
I/O port 3 /A/D analog voltage input
4-bit CMOS I/O ports. Input and output can be programmed in 1-bit units. Pins P2-0 to P3-3 are also used for the built-in 8-bit, 8-channel AD converter analog input. The built-in AD converter uses a successive comparison system. When using a 4.5 MHz oscillator, the conversion clock can be selected from among 900 kHz, 100 kHz, and 50 kHz. When using a 75 kHz oscillator, the conversion clock is set to 75 kHz. The conversion times are respectively 23, 192, 382, and 294 s. The necessary pins can be programmed to A/D analog input in 1-bit units. Voltage up to the VDD can be input as the AD converter analog input voltage. Settings for the AD converter and its associated control can be performed by software. 4-bit CMOS I/O ports. Input and output can be programmed in 1-bit units. Pins P4-1 to P4-3 also input/output the two serial interface circuits (SIO1, SIO2). On the clock edge of the SCK1 pin, SIO1 can input 4-bit or 8-bit serial data to pin SI1 or input/output data to pin SO1. For the serial operation clock (SCK1), an internal (SCK = 37.5 kHz) or external clock can be selected. This design facilitates LSI control and communication between controllers. Enabling the SIO1 interrupt jumps the program to address 4 when SIO1 execution is complete. On the falling edge of the SCK2 pin, SIO2 can input 26-bit serial data to the SI2 pin. SIO2 incorporates a data detector. Enabling the SIO2 interrupt triggers the interrupt on the falling edge of the SCK2 pin and jumps the program to address 6. The SIO1 and SIO2 inputs all incorporate Schmitt circuits. SIO1 and SIO2 and their associated controls can be operated and set by software.
~ ~
VDD
To AD converter Input instruction
VDD
57 58
P4-0 P4-1 /SI1 /SI2 P4-2 /SO1 /SO2 P4-3 /SCK1 /SCK2
I/O port 4 Serial data input 1 /Serial data input 2
Input instruction (P4-0)
59
Serial data input/output 1 /Serial data input 2 Serial clock input/output 1 /Serial clock input 2
VDD
60
Input instruction + SIOon (P4-1~P4-3)
5
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TC93P24FG
Pin No. Symbol Pin Name Function and Operation Remarks
61 62 63
P5-0/BUZR P5-1 /SI3 P5-2 /SO3 /SO4 P5-3 /SCK3 /SCK4
I/O port 5 /buzzer output /Serial data input 3 /Serial data input/output 3 /Serial data input/output 4 /Serial clock input/output 3 /Serial clock input/output 4
64
4-bit CMOS I/O ports. Input and output can be programmed in 1-bit unit. Pin 5-0 is also used to output a buzzer signal. Pins P5-1 to P5-3 are also VDD used to input/output the two serial interface circuits (SIO3, SIO4). The buzzer output can be selected from eight frequency settings (0.625 to 3 kHz), which can be output in four modes: Continuous, Single-Shot, 10 Hz-Intermittent, and 10-Hz Intermittent at 1-Hz Intervals. SIO3 is a serial interface supporting Input instruction three lines, while the SIO4 serial (P5-0) interface supports two lines. On the clock edge of the SCK3/SCK4 pin, SIO3/SIO4 can input 4- or 8-bit serial data to pin SI3 or output data to the SO3/SO4 pin. For the serial operating clock (SCK3/SCK4), an internal (450/225/150/75 kHz) clock or VDD external clock can be selected. Rising and falling shift can also be selected. The clock data output is N-channel open drain. This design facilitates LSI control and communication between controllers. Enabling the SIO3 or SIO4 interrupts triggers the interrupt and jumps the program to address 3 when interface Input instruction + SIOon SIO3 or SIO4 completes execution. (P5-1~P5-3) This is effective for high-speed serial communications. The SIO3 and SIO4 inputs all incorporate Schmitt circuits. SIO3, SIO4, and their associated controls can be used and set by software. 1-bit output port. Normally used as a muting control signal output. This pin can set the internal MUTE bit to 1 according to changes in the I/O port 8 input and HOLD input. The MUTE bit output logic can be changed.
VDD
65
MUTE
Muting output port
66
TEST
Test mode control input
Input pin for controlling Test mode. When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). RIN2
VDD
6
2006-08-31
TC93P24FG
Pin No. Symbol Pin Name Function and Operation Input pin for requesting and releasing Hold mode. Normally used to input radio mode selection or battery detection signals. Hold mode includes Clock Stop mode (crystal oscillator stopped) and Wait mode (CPU stopped), which can be set by the CKSTP and WAIT instructions respectively. Clock Stop mode can be entered by software in one of two ways: on command or when Low level is detected on the HOLD pin. Clock Stop mode can be released when High level is detected on the HOLD pin or when the input changes. Executing the CKSTP instruction stops the clock generator and CPU, entering memory backup mode. In this state the device is set to low current dissipation (10 A max). Wait mode is executed, regardless of the HOLD pin input state, and the device is set to low current dissipation. To set wait mode, specify by software either crystal oscillator only operating or CPU suspended. Wait mode is released when the HOLD pin input changes. External interrupt input pins. Enabling the interrupt function and inputting a pulse (of at least 1.11 to 3.33 s when the 4.5 MHz clock is in use, or at least 13.3 to 40 s when the 75 kHz clock used) to these input pins generates an interrupt (INTR1/2) and jumps the program to address 1/2. The input logic and the clock edge (rising/falling) can be individually selected for each interrupt input. The internal 8-bit timer clock can be selected as input to the pins. At the pulse count or when the count reaches a specified value, an interrupt can be generated (to address 5). These pins are also used to input an 8-bit pulse counter. This counter can be selected from either rising and falling edge input, or an up-counter and a down-counter. These pins are Schmitt inputs and can also be used as input ports. The pins can also be utilized as ports for inputting remote control signals or tape counts. Remarks
VDD
67
HOLD
Hold mode control input
VDD
68 69
INTR1 INTR2 /PCTRin
External interrupt input /pulse count input
7
2006-08-31
TC93P24FG
Pin No. Symbol Pin Name Function and Operation IF signal input pins for the IF counter to count the IF signals of the FM and AM bands and detect the automatic stop position. The input frequency is in the range 0.3 to 20 MHz. A built-in input amp and capacitive coupling support low-amplitude operation. The IF counter is a 20-bit counter with selectable gate times of 1, 4, 16, and 64 ms. 20 bits of data can be easily stored in memory. In Manual mode, the gates can be switched on and off by instruction. These input pins can also be programmed as an input port (IN port). In this case, they become CMOS inputs and the clocks of those inputs can be counted using the IF counter. Note: Pins set as IF input go Low in PLL Off mode. Programmable counter input pins for the FM/AM band. Their input mode can be switched by software from either 1/2 + pulse swallow (VHF/FM) mode for FM input, or pulse swallow (HF) or direct division (LF) mode for AM input. The local oscillation output (voltage-controlled oscillator or VCO output) is normally input at the following frequencies: 50 to 230 MHz in VHF mode, 50 to 140 MHz in FM1 mode, 10 to 60 MHz in FM2 mode, 1 to 30 MHz in HF mode, and 0.5 to 20 MHz in LF mode. A built-in input amp and capacitive coupling support low-amplitude operation. Note: In PLL Off mode or when the pins are not set for input, the input goes to high impedance. Remarks
RFIN VDD
70 71
IFIN1/IN1 IFIN2/IN2
IF signal inputs /input port
RFIN VDD
73
FMIN
FM local oscillation signal input
RFIN VDD
74
AMIN
AM local oscillation signal input
75
VPLL
Constant voltage output for the PLL. The PLL constant voltage is used as the power supply for the PLL and IF counter. In PLL On mode, the PLL constant voltage constant voltage power supply is 3.55 output V (typ.). In PLL Off mode, the VDD is output. Connecting a capacitor (0.1 F, 10 F typ.) stabilizes the power supply.
VPLL
8
2006-08-31
TC93P24FG
Pin No. Symbol Pin Name Function and Operation PLL phase comparator output pins. In tri-state output, when the programmable counter divider output is higher than the reference frequency, the pins output High level; when the output is lower than the reference frequency, the pins output Low level. When the outputs match, the pins go to high impedance. Because DO1 and DO2 are output in parallel, optimal filter constants can be designed for both the AM and FM bands. The DO2 pin can be programmed to high impedance or set as an output port (OUT). Therefore, lockup time can be improved using the DO1 and DO2 pins or the pins can be effectively used as output ports. Lock-up time can also be improved by using DO1 and DO2 together by setting the pins to High-Speed Lock mode when using a 4.5 MHz oscillator. When the phase difference equals or exceeds 1.11 s, DO1 and DO2 output the phase difference pulse. When the phase difference is less than 1.11 s, the DO2 output goes to high impedance and only DO1 outputs the phase difference pulse. Input pin for controlling Test mode. When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). RIN2 Remarks
VDD
77 78
DO1 DO2/OUT
Phase comparator output /output port
VDD
79
TEST2
Test mode control input 2
P6-0 80~83 I/O port 6 P6-3
4-bit CMOS I/O ports. Input and output can be programmed in 1-bit units.
VDD
P7-0 84~87 I/O port 7 P7-3
P8-0 88~91 I/O port 8 P8-3
~ ~ ~
Input instruction
4-bit CMOS I/O port. Input and output can be programmed in 1-bit units. As the pins can be pulled up or pulled down by software they can be used as key input pins. When set to an I/O port input, that input can be varied to release Clock Stop or Wait modes or to set the MUTE bit of the MUTE pin to 1. RIN1
VDD
VDD
VDD
9
2006-08-31
TC93P24FG
Pin No. Symbol Pin Name Function and Operation Constant voltage output pin for the CPU or oscillators. In normal mode, a constant voltage power supply of 2.95 V (typ.) is output; in Clock Stop mode, VDD is output. Connecting a capacitor (0.1 F, 10 F typ.) stabilizes the power supply. Crystal oscillator pins. Connect a 4.5 MHz crystal (Ci = Co = 30 pF typ.) to XIN1 and XOUT1 and a 75 kHz crystal (Ci = Co = 30 pF typ.) to XIN2 and XOUT2. Two different types of crystal resonators (4.5 MHz and 75 kHz) can be connected, or simply connect one (either 4.5 MHz or 75 kHz). Note that if a 75 kHz crystal only is connected, XIN1 must be fixed to GND level. If a 4.5 MHz crystal only is connected, it is not necessary to fix the 75 kHz crystal oscillator pins. If both 4.5 MHz and 75 kHz crystal oscillators are connected, after a reset the CPU operates on the 4.5 MHz crystal oscillator clock. The clock can be readily switched by software between the CPU operating clock and the peripheral clock. Oscillation stops during execution of the CKSTP instruction. Remarks
VCPU
92
VCPU
CPU constant voltage output
XOUT2
ROUT2 RfXT2 VDD
94
XOUT2
75 kHz crystal oscillator pins
XIN2
95
XIN2
XOUT1
ROUT1 RfXT1 VDD
97
XOUT1
4.5 MHz crystal oscillator pins
XIN1
98
XIN1
100
VEE
LCD driver bias voltage output pin
This is the bias voltage output pin for the LCD driver. Pins used for supplying power. In PLL On mode, the pins supply VDD = 4.0 to 5.5 V; in PLL Off mode, the pins supply VDD = 3.5 to 5.5 V. In backup state (on execution of the CKSTP instruction), current dissipation becomes low (10 A max), reducing the power supply voltage to 2.0 V. If 3.5 V or more is applied to these pins when the voltage is 0 V, a system reset is applied to the device and the program starts from address 0 (power-on reset). Note: To operate the power-on reset, allow 10 to 100 ms while the device power supply voltage rises.
39 56 76 96
VDD1 VDD2 VDD3 VDD4
VDD
Power supply pins 41 55 72 93 99 GND1 GND2 GND3 GND4 GND5
GND
10
2006-08-31
TC93P24FG
Absolute Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage VPP Power supply voltage Input voltage 1 Input voltage 2 Input voltage 3 Power dissipation Operating temperature Storage temperature Symbol VDD VPP VIN1 (*) VIN2 (*) VIN3 (*) PD Topr Tstg Rating Unit V V V V V mW C C
-0.3~6.0 -0.3~13.0 -0.3~VCPU + 0.3 -0.3~VPLL + 0.3 -0.3~VDD + 0.3
400
-40~85 -65~150
*: VIN1: Includes XIN1, XOUT1, XIN2, and XOUT2 pins VIN2: Includes AMin, FMin, IFin1, IFin2 (when IF input set) pins VIN3: Input pins, apart from VIN1 and VIN2
Electrical Characteristics (unless otherwise specified, Ta = -40~85C, VDD = 3.5~5.5 V)
Characteristics Operating power supply voltage range Memory hold voltage range Symbol VDD1 VDD2 VHD IDD1 Test Circuit Test Condition When CPU operating When PLL operating Crystal oscillation stopped (CKSTP instruction executed) When PLL operating (VHF mode) and at FMin = 230 MHz input, Ta = 25C When CPU only operating (4.5-MHz clock operating, 75-kHz oscillation stopped, PLL off, display lit), Ta = 25C When CPU only operating (75-kHz clock operating, 4.5-MHz oscillation stopped, PLL off, display lit), Ta = 25C In Hard Wait mode (4.5-MHz crystal only operating), Ta = 25C In Hard Wait mode (75-kHz crystal only operating), Ta = 25C When soft wait executed (PLL off, CPU operating intermittently on 4.5-MHz clock, display lit), Ta = 25C When soft wait executed (PLL off, CPU operating intermittently on 75-kHz clock, display lit), Ta = 25C Crystal oscillator stopped (CKSTP instruction executed) Crystal oscillator 1 (XIN1, XOUT1) Crystal oscillator 2 (XIN2, XOUT2) Crystal oscillator fXT2 = 75 kHz (XIN2, XOUT2) GND reference (VCPU) GND reference (VPLL), VDD = 4.0 to 5.5 V (VCPU), STOP F/F bit detected Min 3.5 4.0 2.0 Typ. ~ ~ ~ 3 Max 5.5 5.5 5.5 5 V Unit V

IDD2
1.0
1.5
mA
IDD3
0.3
0.5
Operating power supply current
IDD4
200
IDD5
70
A
IDD6
350
IDD7
250
Memory hold current
IHD fXT1

2.65 3.15 2.15
0.1 4.5 75
10
A
MHz kHz s V V V

1.0 3.25 3.95 2.65
Crystal oscillator frequency fXT2 Crystal oscillation startup time Constant voltage power supply voltage for CPU Constant voltage power supply voltage for PLL Low voltage detection voltage tst VCPU VPLL VSTOP
2.95 3.55 2.40
11
2006-08-31
TC93P24FG
Programmable Counter and IF Counter Operating Frequency Ranges
Characteristics FMin (VHF mode) FMin (FM mode) fFM2 AMin (HF mode) AMin (LF mode) IFIN1, IFIN2 fHF fLF fIF Symbol fVHF fFM1 Test Circuit Test Condition VIN = 0.2 Vp-p, VDD = 4.0~5.5 V VIN = 0.1 Vp-p, VDD = 4.0~5.5 V VIN = 0.1 Vp-p, VDD = 4.0~5.5 V VIN = 0.1 Vp-p, VDD = 4.0~5.5 V VIN = 0.1 Vp-p, VDD = 4.0~5.5 V VIN = 0.1 Vp-p, VDD = 4.0~5.5 V Min 50 50 10 1.0 0.5 0.3 Typ. ~ ~ ~ ~ ~ ~ Max 230 140 60 30 20 20 MHz Unit

Programmable Counter and IF Counter Input Oscillation Ranges
Characteristics FMin (VHF mode) FMin (FM mode) AMin (HF mode) AMin (LF mode) IFIN1, IFIN2 Symbol VVHF VFM VHF VLF VIF Test Circuit Test Condition fVHF, VDD = 4.0~5.5 V fFM1/fFM2, VDD = 4.0~5.5 V fHF, VDD = 4.0~5.5 V fLF, VDD = 4.0~5.5 V fIF, VDD = 4.0~5.5 V Min 0.2 0.1 0.1 0.1 0.1 Typ. ~ ~ ~ ~ ~ Max 1.0 1.0 1.0 1.0 1.0 Vp-p Unit

LCD Common Outputs/Segment Outputs (COM~COM4, S1~S22)
Characteristics GND level 1/3 VDD level Bias output voltage 1/2 VDD level 2/3 VDD level VDD level Symbol VBS1 VBS2 VBS3 VBS4 VBS5 Test Circuit Test Condition VDD = 5 V, no load VDD = 5 V, no load VDD = 5 V, no load VDD = 5 V, no load VDD = 5 V, no load Min Typ. 0.00 1.67 2.50 3.33 5.00 Max 0.15 1.82 2.65 3.48 V Unit

1.52 2.35 3.18 4.85
Output Ports and I/O Ports (OT1~OT30, P1-0~P10-3)
Characteristics High level Output current Symbol IOH1 IOL1 Low level IOL2 Input leakage current High level Input voltage Low level Input pulled-up/down resistor VIL RIN1 ILI VIH Test Circuit Test Condition VDD = 5 V, VOH = VDD - 0.5 V VDD = 5 V, VOL = 0.5 V, except for P5-1 to P5-3 VDD = 5 V, VOL = 0.5V, P5-1~P5-3 VIH = VDD, VIL = 0V (P1-0~P10-3) (P1-0~P10-3) (P1-0~P10-3) When P8-0 to P8-3 pulled up/down Min Typ. Max Unit

-1.00
1.00 4.00
-2.50
2.50 10.00
1.0
VDD VDD x 0.2 250 V mA
VDD x 0.8 0 15
~ ~ 60
A
k
12
2006-08-31
TC93P24FG
MUTE, DO1, DO2 Output
Characteristics Output current High level Low level Symbol IOH1 IOL1 ITL Test Circuit Test Condition VDD = 5 V, VOH = VDD - 0.5 V VDD = 5 V, VOL = 0.5 V VDD = 5 V, VTLH = 5 V, VTLL = 0 V (DO1, DO2) Min Typ. Max Unit mA

-1.25
1.25
-2.50
2.50
100
Output off leakage current
nA
HOLD , INTR1/2, IN1/2 Input Ports, RESET Input
Characteristics Input leakage current High level Output current Low level Symbol ILI VIH VIL Test Circuit Test Condition VIH = VDD, VIL = 0 V Min Typ. Max Unit

VDD x 0.8 0
~ ~
1.0
VDD VDD x 0.2
A

V
AD Converter (ADIN1~ADIN8, DCREF)
Characteristics Analog input voltage range Resolution Linear error Conversion total error Analog input leakage Reference voltage input current Symbol VAD VRES Test Circuit Test Condition ADin1~ADin8 Min 0 Typ. ~ 8 Max VDD Unit V bit LSB

VDD = 5 V, DCREF = 5 V VDD = 5V, VIH = 5V, VIL = 0 V (ADin1~ADin8) VDD = 5V, DCREF = 5 V (DCREF)

1.0 8.0 1.0
1.0

ILI IREF
0.5 3.0
0.5
A
mA
Crystal Oscillators
Characteristics XIN1 amp feedback resistance XIN2 amp feedback resistance XOUT1 output resistance XOUT2 output resistance Symbol RfXT1 RfXT2 ROUT1 ROUT2 Test Circuit Test Condition (XIN1-XOUT1) (XIN2-XOUT2) (XOUT1) (XOUT2) Min 0.35 3.5 1.2 1.5 Typ. 1.0 10 3.0 4.0 Max 3.00 30.0 10.0 k 15.0 Unit M

Others
Characteristics Input pulled-down resistance Input amp feedback resistance Symbol RIN2 RfIN Test Circuit Test Condition (TEST) VPLL = 3.5 V (FMin, AMin, IFin1, IFin2) Min 15.0 350 Typ. 60 800 Max 250 k 3500 Unit

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2006-08-31
TC93P24FG
Package Dimensions
Weight: 1.6 g (typ.) Note: Lead type PD-Pff
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2006-08-31
TC93P24FG
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E
15
2006-08-31

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